Increasing NoC power estimation accuracy through a rate-based model
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A high abstraction, high accuracy power estimation model for networks-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Explicit modeling of control and data for improved NoC router estimation
Proceedings of the 49th Annual Design Automation Conference
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Journal of Electronic Testing: Theory and Applications
Design space exploration of thermal-aware many-core systems
Journal of Systems Architecture: the EUROMICRO Journal
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The increasing use of mobile electronic devices forces the design of integrated circuits to consider low power techniques. Current power estimation models for NoCs capitalize mostly in the volume of information transmitted through the network. This work presents a more precise NoC power estimation model, based in buffer reception rates, according to the traffic scenario applied to the network. Results show the accuracy of the model compared to industrial power estimation tools, with reduced execution time. The proposed method allows exploring the NoC design space, being employed to evaluate the benefit on using the multicast service.