Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
NoC Power Estimation at the RTL Abstraction Level
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
Addressing thermal and power delivery bottlenecks in 3D circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A multi-objective strategy for concurrent mapping and routing in networks on chip
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication
PDP '11 Proceedings of the 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing
Enhancing Performance of NoC-Based Architectures Using Heuristic Virtual-Channel Sharing Approach
COMPSAC '11 Proceedings of the 2011 IEEE 35th Annual Computer Software and Applications Conference
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CoNA: Dynamic application mapping for congestion reduction in many-core systems
ICCD '12 Proceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)
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Higher temperatures or uneven distribution of temperatures result in timing uncertainties which induces performance and reliability concerns for the system. Future 3D IC technology offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. However, 3D technology exacerbates the on-chip thermal issues and increases packaging and cooling costs. In order to resolve these issues in 2D and 3D systems, and avoid high and uneven temperatures, accurate thermal modeling and analysis, and thermal-aware placement optimizations are essential before tapeout. In this paper, we propose a thermally efficient routing strategy for 3D NoC-Bus Hybrid architectures, which mitigates on-chip temperatures by conducting most of the switching activity closer to the heat sink. Our simulations with a real world benchmark show that there has been a significant decrease in the peak temperatures when compared to a typical stacked mesh 3D NoC. Also, we have presented an exploration of various thermal-aware placement approaches for both the 2D and 3D stacked systems. Various thermal models have been developed in order to investigate the effect of thermal-aware placement in 2D chip and 3D stacked systems. Using the developed metrics, we proposed an efficient thermal-aware application mapping for a 2D NoC. Steady-state simulations show that the proposed thermal-aware mapping algorithm reduces the effective chip area reeling under high temperatures when compared to the Tree-Model-Based (TMB) mapping and Worst case mapping.