Analysis of power consumption on switch fabrics in network routers
Proceedings of the 39th annual Design Automation Conference
Orion: a power-performance simulator for interconnection networks
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Power constrained design of multiprocessor interconnection networks
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Leakage power modeling and optimization in interconnection networks
Proceedings of the 2003 international symposium on Low power electronics and design
Flow control and micro-architectural mechanisms for extending the performance of interconnection networks
A Power and Performance Model for Network-on-Chip Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
A low-power crossroad switch architecture and its core placement for network-on-chip
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
The design and implementation of a low-latency on-chip network
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
NoCEE: energy macro-model extraction methodology for network on chip routers
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A High Level Power Model for the Nostrum NoC
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
A Power and Energy Exploration of Network-on-Chip Architectures
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NoC Power Estimation at the RTL Abstraction Level
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
A high level power model for Network-on-Chip (NoC) router
Computers and Electrical Engineering
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Improved on-chip router analytical power and area modeling
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Accurate Machine-Learning-Based On-Chip Router Modeling
IEEE Embedded Systems Letters
Enhanced metamodeling techniques for high-dimensional IC design estimation problems
Proceedings of the Conference on Design, Automation and Test in Europe
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Networks-on-Chip (NoCs) are scalable fabrics for interconnection networks used in many-core architectures. ORION2.0 is a widely adopted NoC power and area estimation tool; however, its models for area, power and gate count can have large errors (up to 110% on average) versus actual implementation. In this work, we propose a new methodology that analyzes netlists of NoC routers that have been placed and routed by commercial tools, and then performs explicit modeling of control and data paths followed by regression analysis to create highly accurate gate count, area and power models for NoCs. When compared with actual implementations, our new models have average estimation errors of no more than 9.8% across microarchitecture and implementation parameters. We further describe modeling extensions that enable more detailed flit-level power estimation when integrated with simulation tools such as GARNET.