Fault-tolerant architecture and deflection routing for degradable NoC switches
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A high level power model for Network-on-Chip (NoC) router
Computers and Electrical Engineering
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Explicit modeling of control and data for improved NoC router estimation
Proceedings of the 49th Annual Design Automation Conference
Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes
Microprocessors & Microsystems
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We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. The model, which from now on will be called Nos-HPM (Nostrum High-Level Power Model) allows a fast power analysis and is accurate within 5%. System simulations with Nos-HPM run up to 500 times faster than with Power Compiler for a 4 x 4 network. We find a maximum power consumption of 0.7 W for a 4 x 4 mesh and 3.5 W for an 8 x 8 mesh, both implemented in 0.18ìm UPC CMOS technology. In the worst case the average energy per cycle for a 128-bit packet is 508 pJ, while it is 20 pJ for a payload byte. The power consumption of all the links is equivalent or slightly higher than the power consumption of all the switches. A comparison between our results and some related work is also presented.