Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels

Authors:
Amir-Mohammad Rahmani;Kameswar Rao Vaddina;Pasi Liljeberg;Juha Plosila;Hannu Tenhunen
Affiliations:
Computer Systems Lab., Department of Information Technology, University of Turku, Finland and Turku Centre for Computer Science, Finland;Computer Systems Lab., Department of Information Technology, University of Turku, Finland and Turku Centre for Computer Science, Finland;Computer Systems Lab., Department of Information Technology, University of Turku, Finland;Computer Systems Lab., Department of Information Technology, University of Turku, Finland;Computer Systems Lab., Department of Information Technology, University of Turku, Finland
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

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Abstract

3D NoC offers greater device integration, faster vertical interconnects and more power efficient inter-layer communication due to the beneficial attribute of short through silicon via (TSV) in 3D IC technologies. However, TSV pads used for bonding to a wafer layer, occupy significant chip area and result in routing congestions and expensive manufacturing process. This can lead to a significant reduction in 3D ICs' yield and higher power densities compared to 2D NoCs. In this paper, a power-efficient and low-cost inter-layer communication scheme is proposed as one way to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a high-performance bidirectional channel enables a system to benefit from low-latency nature of the vertical interconnects and to remarkably reduce the number of TSVs. Additionally, we present a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication. Our extensive simulations demonstrate significant area and power improvements compared to a typical symmetric 3D NoC.