Communications of the ACM
Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Interfacing synchronous and asynchronous modules within a high-speed pipeline
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
A FIFO Ring Performance Experiment
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Robust interfaces for mixed-timing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Computing synchronizer failure probabilities
Proceedings of the conference on Design, automation and test in Europe
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Practical asynchronous interconnect network design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchronization and Arbitration in Digital Systems
Synchronization and Arbitration in Digital Systems
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2nd International Workshop on Network on Chip Architectures
Proceedings of the 7th ACM international conference on Computing frontiers
Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
Journal of Computer and System Sciences
| Hi-index | 0.00 |
Systems-on-chip designs often use functional blocks operating at different clock frequencies. This motivates the use of an asynchronous network-on-chip (NoC) with synchronizing FIFOs interfacing between the NoC and the functional blocks. To minimize design time, these FIFOs should be constructed from cells available in a standard cell library and configurable to work in a wide range of applications. We present a modular synchronizing FIFO design that can be implemented using logic gates from a typical standard-cell library. The FIFO has interchangeable input and output interfaces for edge-triggered synchronous communication and for two asynchronous handshake protocols: asP* and LEDR. The FIFO capacity, synchronizer latency and interface protocols are independent parameters, allowing the FIFO to be easily configured for different NoC requirements. We evaluate performance using post-layout simulation results and analyze the metastability induced failure rate for synchronization latencies from half a clock cycle up to three clock cycles.