A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction

Authors:
Amir Ehsani Zonouz;Mehrdad Seyrafi;Arghavan Asad;Mohsen Soryani;Mahmoud Fathy;Reza Berangi
Affiliations:
-;-;-;-;-;-
Venue:
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Year:
2009

A power-efficient network on-chip topology

Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings

Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip

Journal of Electronic Testing: Theory and Applications

Hi-index	0.00