Low power nanoscale buffer management for network on chip routers

Authors:
Suman K. Mandal;Ron Denton;Saraju P. Mohanty;Rabi N. Mahapatra
Affiliations:
Texas A&M University, College Station, TX, USA;Texas A&M University, College Station, TX, USA;University of North Texas, Denton, TX, USA;Texas A&M University, College Station, TX, USA
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

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Abstract

Network-on-Chip (NoC) is an on-chip communication solution in the future system-on-a-chip (SoC) necessitating high performance operation with low power dissipation. We present a novel dynamic power management technique for low power NoC router buffers using nano CMOS SRAMS. A feedback controller was designed for block level power management and a power aware adaptive controller was designed for low power flit storage encoding to reduce energy consumptions in the router buffers. Experiments with the proposed scheme showed up to 20% reduction in energy consumption while improving throughput by up to 21%.