Automatic phase detection for stochastic on-chip traffic generation
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Long-range dependence and on-chip processor traffic
Microprocessors & Microsystems
Comprehensive on-chip traffic generator model for SoC design and synthesis
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
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We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three important characteristics: the splitting of traffic generation in multiple phases, the ability to replay a previously recorded trace in various interconnect systems, and the capacity to produce stochastic traffic with advanced statistical properties. We focus here on the second characteristics, by validating it in cycle-accurate SystemC simulations.