Adaptive router architecture based on traffic behavior observability
Proceedings of the 2nd International Workshop on Network on Chip Architectures
A NOC closed-loop performance monitor and adapter
Microprocessors & Microsystems
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Network topology and routing are key problems for the design of Network on chip (NoC). The paper discusses how to choose suitable topology and node encoding scheme for NoC, and proposes a two-dimensional plane code based on Johnson Code by the combination of network topology with corresponding node coding. The node coding implies the relation between neighbouring nodes and their links and the global information of routing. Utilizing the code, the improved algorithm for X-Y routing is presented, which is implemented with only two or three logic operations in middle nodes. The experimental results show that the combination of the code proposed with Torus topology can simplify the routing algorithm in the implementation of NoC and significantly decrease signal latency and greatly improve communication performance.