Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Micro-Genetic Algorithm for Multiobjective Optimization
EMO '01 Proceedings of the First International Conference on Evolutionary Multi-Criterion Optimization
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hardware architecture for genetic algorithms
IEA/AIE'2005 Proceedings of the 18th international conference on Innovations in Applied Artificial Intelligence
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A comparison of two circuit representations for evolutionary digital circuit design
IEA/AIE'2004 Proceedings of the 17th international conference on Innovations in applied artificial intelligence
A Multi-Objective Evolutionary Algorithm Based Optimization Model for Network-on-Chip Synthesis
ITNG '07 Proceedings of the International Conference on Information Technology
Muiltiobjective optimization using nondominated sorting in genetic algorithms
Evolutionary Computation
An Evolutionary Metaheuristic for Approximating Preference-Nondominated Solutions
INFORMS Journal on Computing
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Compact yet efficient hardware implementation of artificial neural networks with customized topology
Expert Systems with Applications: An International Journal
Static routing for applications mapped on NoC platform using ant colony algorithms
International Journal of High Performance Systems Architecture
Hi-index | 12.05 |
Network-on-chip (NoC) are considered the next generation of communication infrastructure in embedded systems. In the platform-based design methodology, an application is implemented by a set of collaborative intellectual property (IP) blocks. The selection of the most suited set of IPs as well as their physical mapping onto the NoC infrastructure to implement efficiently the application at hand are two hard combinatorial problems that occur during the synthesis process of Noc-based embedded system implementation. In this paper, we propose an innovative preference-based multi-objective evolutionary methodology to perform the assignment and mapping stages. We use one of the well-known and efficient multi-objective evolutionary algorithms NSGA-II and microGA as a kernel. The optimization processes of assignment and mapping are both driven by the minimization of the required silicon area and imposed execution time of the application, considering that the decision maker's preference is a pre-specified value of the overall power consumption of the implementation.