Integrating dynamic thermal via planning with 3D floorplanning algorithm
Proceedings of the 2006 international symposium on Physical design
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Thermal analysis of a 3D die-stacked high-performance microprocessor
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
PCRAMsim: system-level performance, energy, and area modeling for phase-change ram
Proceedings of the 2009 International Conference on Computer-Aided Design
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC
Proceedings of the 16th Asia and South Pacific Design Automation Conference
ACM SIGARCH Computer Architecture News
3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling
Proceedings of the International Conference on Computer-Aided Design
Towards Thermal Profiling in CMOS/Memristor Hybrid RRAM Architectures
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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3D-ICs hold significant promise for future generation multi processor systems-on-chip due to their potential for increased performance, decreased power, heterogeneous integration, and reduced cost over planar ICs. However, the vertical integration of these structures exacerbates the heat dissipation and run-time thermal management issues. There have been a number of design- and run-time thermal management policies proposed, but few focus on examining overall system performance. Additionally, the heterogeneity of 3D-ICs allows for the integration of novel technologies, such as resistive random access memories (RRAMs), which offer higher density and lower power than traditional CMOS memory technologies. Our work presents a flexible design-time simulation framework to evaluate system performance and thermal profiles of 3D MPSoCs. We utilize this framework to study the effect of three dynamic thermal management policies (air-cooled load balancing, liquid-cooled load balancing, and air-cooled DVFS) on system performance and die temperature for multi-tiered 3D MPSoCs utilizing SRAM and RRAM-based L2 caches. We find that RRAM-based caches lower overall average maximum temperatures by 120 K and 24 K for air and liquid cooling systems, respectively (when compared to SRAM-based caches), at a worst-case performance delay of 47% and best-case delay of 13% for the parallel shared-memory benchmarks studied.