Structure theory of Petri nets: the free choice hiatus
Advances in Petri nets 1986, part I on Petri nets: central models and their properties
A Generalized Timed Petri Net Model for Performance Analysis
IEEE Transactions on Software Engineering
Some classes of live and safe Petri nets
Concurrency and nets: advances in Petri nets
Simulation output analysis using standardized time series
Mathematics of Operations Research
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Theoretical Computer Science
A technique of state space search based on unfolding
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
Verification of asynchronous circuits using time Petri net unfolding
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Approximate algorithms for time separation of events
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A Course in Simulation
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Performance Analysis and Optimization of Asynchronous Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Efficient Timing Analysis of a Class of Petri Nets
Proceedings of the 7th International Conference on Computer Aided Verification
Linear Time, Branching Time and Partial Order in Logics and Models for Concurrency, School/Workshop
Verification of Timed Systems Using POSETs
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Response Time Properties of Some Asynchronous Circuits
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Estimation Methods for Stochastic Petri Nets Based on Standardized Time Series
PNPM '97 Proceedings of the 6th International Workshop on Petri Nets and Performance Models
Markovian analysis of large finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient state classification of finite-state Markov chains
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accelerating Markovian analysis of asynchronous systems using state compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Symbolic Analysis of Bounded Petri Nets
IEEE Transactions on Computers
Reducing probabilistic timed petri nets for asynchronous architectural analysis
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fundamenta Informaticae - Application of concurrency to system design
Temporal Properties of Self-Timed Rings
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Performance Analysis of Asynchronous Circuits Using Markov Chains
Concurrency and Hardware Design, Advances in Petri Nets
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Global critical path: a tool for system-level timing analysis
Proceedings of the 44th annual Design Automation Conference
An efficient algorithm for time separation of events in concurrent systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Operation chaining asynchronous pipelined circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Modular performance analysis of cyclic dataflow graphs
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Characterizing asynchronous variable latencies through probability distribution functions
Microprocessors & Microsystems
High performance asynchronous design flow using a novel static performance analysis method
Computers and Electrical Engineering
Synthesis and optimization of pipelined packet processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process variation-aware performance analysis of asynchronous circuits
Microelectronics Journal
Accurate performance estimation for stochastic marked graphs by bottleneck regrowing
EPEW'10 Proceedings of the 7th European performance engineering conference on Computer performance engineering
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Fundamenta Informaticae - Application of Concurrency to System Design
| Hi-index | 0.00 |
This paper presents a technique to estimate the average time separation of events (TSE) in stochastic timed Petri nets that can model time-independent choice and have arbitrary delay distributions associated with places. The approach analyzes finite net unfoldings to derive closed-form expressions for lower and upper bounds on the average TSE, which can be efficiently evaluated using standard statistical methods. The mean of the derived upper and lower bounds thus provides an estimate of the average TSE which has a well-defined error bound. Moreover, we can often make the error arbitrarily small by analyzing larger net unfoldings at the cost of additional run-time. Experiments on several asynchronous systems demonstrate the quality of our estimate and the efficiency of the technique. The experiments include the performance analysis of a full-scale Petri net model of Intel's asynchronous instruction length decoding and steering unit RAPPID containing over 900 transitions and 500 places.