Communications of the ACM
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Performance analysis based on timing simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Focusing processor policies via critical-path prediction
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Slack Matching Asynchronous Designs
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Symbolic timing analysis of asynchronous systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Operation chaining asynchronous pipelined circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Slack analysis in the system design loop
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Synthesis and optimization of pipelined packet processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is defined at the RTL level, as the longest path in the combinational logic between clocked registers. In this paper, we present a system-level timing analysis technique to define the concept of a Global Critical Path (GCP), for predicting system-level performance. We show how the GCP can be used as a theoretical and practical tool for understanding, summarizing and optimizing the behavior of highly concurrent self-timed circuits. We formally define the GCP and show how it can be constructed using a discrete event model and hardware profiling techniques. The GCP provides valuable insight into the control-path behavior of circuits and in finding system-level bottlenecks. We have incorporated the GCP construction and analysis framework into a high-level synthesis and simulation toolchain, thus enabling complete automation in modeling, analysis and optimization.