Worst-case performance analysis of parallel, communicating software processes
Proceedings of the tenth international symposium on Hardware/software codesign
Global critical path: a tool for system-level timing analysis
Proceedings of the 44th annual Design Automation Conference
Synthesis and optimization of pipelined packet processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We extend the time separations of events (TSE) timing analysis algorithm into the symbolic domain, that is, we allow symbolic variables to be used to specify unknown parameters of the model (essentially, unknown delays) and verification algorithms which are capable of identifying not just failure or success, but also the constraints on these symbolic variables which will ensure successful verification. The two contributions are (1) an iterative algorithm which continuously narrows down the domain of interest and (2) a practical method for reducing the representation of symbolic expressions containing minimizations and maximizations defined for a given domain. The algorithm applies to asynchronous circuits without conditional behavior. Although this may seem a severe restriction, this is a large and useful subclass which includes, e,g,, pipeline structures. We report experimental results for several asynchronous circuits to demonstrate that symbolic analysis is feasible and that the output provided is what a designer (or perhaps a synthesis tool) would often want to know