Performance analysis and optimization of asynchronous circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Performance analysis based on timing simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
ACM Transactions on Computer Systems (TOCS)
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Slack Elasticity in Concurrent Computing
MPC '98 Proceedings of the Mathematics of Program Construction
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Network Systems Design Using Network Processors
Network Systems Design Using Network Processors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Mapping a domain specific language to a platform FPGA
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Hyper-Programmable Architectures for Adaptable Networked Systems
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CUSP: a modular framework for high speed network applications on FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Slack Matching Asynchronous Designs
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Slack Matching Quasi Delay-Insensitive Circuits
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Global critical path: a tool for system-level timing analysis
Proceedings of the 44th annual Design Automation Conference
High level synthesis for packet processing pipelines
High level synthesis for packet processing pipelines
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
A throughput-driven task creation and mapping for network processors
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
MPLS and the evolving Internet architecture
IEEE Communications Magazine
Symbolic timing analysis of asynchronous systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Throughput-driven floorplanning with wire pipelining
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance analysis of latency-insensitive systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We consider pipelined architectures of packet processors consisting of a sequence of simple packet-processing modules interconnected by first-in first-out buffers. We propose a new model for describing their function, an automated synthesis technique that generates efficient hardware for them, and an algorithm for computing minimum buffer sizes that allow such pipelines to achieve their maximum throughput. Our functional model provides a level of abstraction familiar to a network protocol designer; in particular, it does not require knowledge of register-transfer-level hardware design. Our synthesis tool implements the specified function in a sequential circuit that processes packet data a word at a time. Finally, our analysis technique computes the maximum throughput possible from the modules and then determines the smallest buffers that can achieve it. Experimental results conducted on industrial-strength examples suggest that our techniques are practical. Our synthesis algorithm can generate circuits that achieve 40 Gb/s on field-programmable gate arrays, equal to state-of-the-art manual implementations, and our buffer-sizing algorithm has a practically short runtime. Together, our techniques make it easier to quickly develop and deploy high-speed network switches.