Performance analysis based on timing simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
A new optimization technique for improving resource exploitation and critical path minization
ISSS '97 Proceedings of the 10th international symposium on System synthesis
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ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Performance evaluation of asynchronous logic pipelines with data dependent processing delays
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Theoretical Limits on the Data Dependent Performance of Asynchronous Circuits
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
Latency and throughput tradeoffs in self-timed speed-independent pipelines and rings
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This paper is devoted to studying two key issues of the asynchronous pipelines: their performance, and the influence that the position of stages have on the latency of a pipelined asynchronous circuit as a whole. To attain the performance evaluation, we derive expressions of the latency and the cycle time of a linear pipeline as closed-form formulas. To attain the influence of the position, we present some experiments, using the previous closed-form formulas, on different pipelines.