Equivalence relations in queueing models of fork/join networks with blocking
Performance Evaluation - Queueing networks with finite capacity queues
VLSI Signal Processing; A Bit-Serial Approach
VLSI Signal Processing; A Bit-Serial Approach
Marking Optimization of Stochastic Timed Event Graphs
Proceedings of the 14th International Conference on Application and Theory of Petri Nets
Performance evaluation of asynchronous logic pipelines with data dependent processing delays
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Bundled Data Asynchronous Multipliers with Data Dependent Computation Times
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems
CSD '98 Proceedings of the 1998 International Conference on Application of Concurrency to System Design
Fundamenta Informaticae - Application of concurrency to system design
Characterizing asynchronous variable latencies through probability distribution functions
Microprocessors & Microsystems
Simulating a LAGS processor to consider variable latency on L1 D-Cache
Proceedings of the 2010 Summer Computer Simulation Conference
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
Fundamenta Informaticae - Application of Concurrency to System Design
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Speculations about the ability of asynchronous systems to take advantage of the data dependent performance of circuit components have been widespread. Simulations and actual designs have not however provided much confirmation that it is possible to transfer the average case data dependent performance of a single stage into average case performance of a system without paying an unacceptable area penalty in the implementation. Here it is shown that if area*time is chosen as the performance metric to be minimized there are in fact absolute theoretical limits to achieving data dependent performance as compared with synchronous circuits. These limits are shown to arise in two completely different theoretical approaches each of which make few assumptions about the distribution of data dependent delays experienced when the circuit operates. The theoretical approach confirms many of the tradeoffs that designers of data dependent circuits have long suspected.