Sim-async: an architectural simulator for asynchronous processor modeling using distribution functions

Authors:
J. M. Colmenar;O. Garnica;J. Lanchares;J. I. Hidalgo;G. Miñana;S. Lopez
Affiliations:
C. E. S. Felipe II, Complutense U. of Madrid;Dept. of Computer Arch. and System Engineering, Complutense U. of Madrid;Dept. of Computer Arch. and System Engineering, Complutense U. of Madrid;Dept. of Computer Arch. and System Engineering, Complutense U. of Madrid;Dept. of Computer Arch. and System Engineering, Complutense U. of Madrid;Dept. of Computer Arch. and System Engineering, Complutense U. of Madrid
Venue:
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
Year:
2006

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Abstract

In this paper we present sim-async, an architectural simulator able to model a 64-bit asynchronous superscalar microarchitecture. The aim of this tool is to serve the designers on the study of different architectural proposals for asynchronous processors. Sim-async models the data-dependant timing of the processor modules by using distribution functions that describe the probability of a given delay to be spent on a computation. This idea of characterizing the timing of the modules at the architectural level of abstraction using distribution functions is introduced for the first time with this work. In addition, sim-async models the delays of all the relevant hardware involved in the asynchronous communication between stages. To tackle the development of sim-async we have modified the source code of SimpleScalar by substituting the simulator's core with our own execution engine, which provides the functionality of a parameterizable microarchitecture adapted to the Alpha ISA. The correctness of sim-async was checked by comparing the outputs of the SPEC2000 benchmarks with SimpleScalar executions, and the asynchronous behavior was successfully tested in relation to a synchronous configuration of sim-async.