Communicating sequential processes
Communicating sequential processes
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
AMULET1: An Asynchronous ARM Microprocessor
IEEE Transactions on Computers
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
Synthesis of 3D Asynchronous State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Delay-Insensitive Circuits: An Algebraic Approach to their Design
CONCUR '90 Proceedings of the Theories of Concurrency: Unification and Extension
Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language
Proceedings of the 12th European Simulation Multiconference on Simulation - Past, Present and Future
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Computer Organization and Design
Computer Organization and Design
A formal approach to designing delay-insensitive circuits
Distributed Computing
CASCADE: a tool kernel supporting a comprehensive design method for asynchronous controllers
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
A Framework for Distributed Simulation of Asynchronous Handshake Circuits
ANSS '06 Proceedings of the 39th annual Symposium on Simulation
Euro-Par'06 Proceedings of the 12th international conference on Parallel Processing
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The last fifteen years have witnessed a resurgence ofinterest in asynchronous digital design techniques as theypromise to liberate VLSI systems from clock skew problems,offer the potential for low power and high performanceand encourage a modular design philosophy whichmakes incremental technological migration a much easiertask. This activity has revealed a need for modelling andsimulation techniques suitable for the asynchronous designstyle. The concurrent process algebra Communication SequentialProcesses (CSP) is increasingly advocated as particularlysuitable for this purpose. This paper discusses themodelling of SAMIPS, a synthesisable asynchronous MIPSprocessor core, in Balsa, a CSP-based, asynchronous hardwaredescription language and synthesis tool.