Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs
SIAM Journal on Scientific Computing
High-performance hardware description language simulation: modeling issues and recommended practices
Transactions of the Society for Computer Simulation International - Special issue on parallel and distributed simulation
Dhrystone: a synthetic systems programming benchmark
Communications of the ACM
Graph partitioning models for parallel computing
Parallel Computing - Special issue on graph partioning and parallel computing
Synthesising an asynchronous DMA controller with balsa
Journal of Systems Architecture: the EUROMICRO Journal
Parallel and Distribution Simulation Systems
Parallel and Distribution Simulation Systems
Distributed simulation of asynchronous hardware: the program driven synchronization protocol
Journal of Parallel and Distributed Computing
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Modelling SAMIPS: A Synthesisable Asynchronous MIPS Processor
ANSS '04 Proceedings of the 37th annual symposium on Simulation
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This paper presents PARBREEZE, a distributed simulation kernel for asynchronous hardware behavioural simulation. PARBREEZE is based on the Logical Process paradigm and targets asynchronous handshake circuits generated by the Balsa asynchronous hardware synthesis environment. The paper describes the architecture of PARBREEZE and presents performance results for different partitioning strategies.