Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Hardware Design and Petri Nets
Hardware Design and Petri Nets
From STG to Extended-Burst-Mode Machines
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Synthesis of asynchronous controllers for heterogeneous systems
Synthesis of asynchronous controllers for heterogeneous systems
Hazard-free implementation of speed-independent circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decomposition in Asynchronous Circuit Design
FST TCS '02 Proceedings of the 22nd Conference Kanpur on Foundations of Software Technology and Theoretical Computer Science
Decomposition in Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
Modelling SAMIPS: A Synthesisable Asynchronous MIPS Processor
ANSS '04 Proceedings of the 37th annual symposium on Simulation
Improved Decomposition of Signal Transition Graphs
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Improved Decomposition of Signal Transition Graphs
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
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CASCADE is a tool kernel that supports the synthesis of asynchronous controllers. It uses a generalized STG (an interpreted Petri net) as a unified design entry and allows the designer to choose between several appropriate design methods. It then transforms the initial specification into the design entry required by the chosen style, and interfaces with existing synthesis tools (petrify for SI circuits, 3D for XBM synthesis). By decomposition, certain problems involving output concurrency and MOC behaviour are made XBM-feasible.