The first asynchronous microprocessor: the test results
ACM SIGARCH Computer Architecture News
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Defining a beta distribution function for construction simulation
Proceedings of the 31st conference on Winter simulation: Simulation---a bridge to the future - Volume 2
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
IEEE Micro
Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language
Proceedings of the 12th European Simulation Multiconference on Simulation - Past, Present and Future
ARAS: asynchronous RISC architecture simulator
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Theoretical Limits on the Data Dependent Performance of Asynchronous Circuits
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
AMULET3i - An Asynchronous System-on-Chip
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A Practical Comparison of Asynchronous Design Styles
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
simCore: An Event-Driven Simulation Framework for Performance Evaluation of Computer Systems
MASCOTS '00 Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems
Practical Design and Performance Evaluation of Completion Detection Circuits
ICCD '98 Proceedings of the International Conference on Computer Design
Correlational and Distributional Effects in Network Traffic Models
IPDS '00 Proceedings of the 4th International Computer Performance and Dependability Symposium
High-performance ULSI: the real limiter to interconnect scaling
Proceedings of the 2005 international workshop on System level interconnect prediction
Recent extensions to the SimpleScalar tool suite
ACM SIGMETRICS Performance Evaluation Review - Special issue on tools for computer architecture research
A traffic characterization of popular on-line games
IEEE/ACM Transactions on Networking (TON)
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
IEEE Computer Architecture Letters
An asynchronous low-power high-performance sequential decoder implemented with QDI templates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
Journal of Computer and System Sciences
ICCS'05 Proceedings of the 5th international conference on Computational Science - Volume Part III
Synthesis of asynchronous controllers using integer linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulating a LAGS processor to consider variable latency on L1 D-Cache
Proceedings of the 2010 Summer Computer Simulation Conference
| Hi-index | 0.00 |
Asynchronous systems are attracting the interest of the designer community because of several useful features for sub-micron technologies: process-variation tolerant, low-power, removal of the clock tree generation, etc. One of the main problems for the simulation of these systems is the variable computation delays of their modules, that compute as fast as possible under the actual conditions of the system. This behavior complicates the high-level simulation of such systems and it is the main reason for the lack of simulation tools devoted to asynchronous microarchitectures. In this paper we present a modeling method useful for this kind of systems that describes the variable computation delay of an asynchronous circuit by using probability distribution functions. This method is deployed in an architectural simulator of a 64-bit superscalar asynchronous microarchitecture where the computation delay of each one of the modules of the microarchitecture was characterized through a probability distribution function. The experimental results show that the asynchronous behavior is successfully modeled, and the architectural simulations of standard benchmarks is affordable in terms of wall-clock simulation time.