Characterizing asynchronous variable latencies through probability distribution functions
Microprocessors & Microsystems
Simulating a LAGS processor to consider variable latency on L1 D-Cache
Proceedings of the 2010 Summer Computer Simulation Conference
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In a classic paper at the 1995 IEEE Electron Devices Meeting, Mark Bohr outlined how interconnect scaling --- specifically, resistance scaling --- will ultimately limit the performance of future ULSI circuits [1]. Looking ahead, we see the reverse: constraints imposed by high-performance VLSI systems will limit how we can design and scale wires.In the ten years since, Bohr's prediction has been borne out by the vast efforts of designers to overcome wire RC delay. Tactics such as inserting repeaters, predicting wire routing and integrating optics have all been analyzed, published, and sometimes even used. As a result, wire latency is manageable using repeaters and wire bandwidth is unparalleled, though wire power can be a problem.However, two important trends in high-performance systems will affect our ability to scale on-chip wire latency and bandwidth. First, VLSI complexity and design costs will increasingly push designers towards modular systems such as multi-core architectures. Second, power density trends stemming from flat voltage scaling constrain how many of our transistors we can use at once, again leading to machines built from selectively-enabled modular units.Such systems present different challenges to on-chip wiring and scaling its latency, power, and bandwidth. Recent work in three-dimensional integration shows promise in these areas but creates problems with system assembly. We will examine characteristics and trends of on-chip interconnects and discuss Proximity Communication, a wireless chip-to-chip communication technology.