Performance analysis and optimization of asynchronous circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Practical applications of an efficient time separation of events algorithm
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Petri Net Theory and the Modeling of Systems
Petri Net Theory and the Modeling of Systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Performance Analysis and Optimization of Asynchronous Circuits
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Slack Elasticity in Concurrent Computing
MPC '98 Proceedings of the Mathematics of Program Construction
Proceedings of the 40th annual Design Automation Conference
High-level synthesis of asynchronous systems by data-driven decomposition
Proceedings of the 40th annual Design Automation Conference
Self-Timed Meshes Are Faster Than Synchronous
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Slack Matching Asynchronous Designs
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Slack Matching Quasi Delay-Insensitive Circuits
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
A new way to enumerate cycles in graph
AICT-ICIW '06 Proceedings of the Advanced Int'l Conference on Telecommunications and Int'l Conference on Internet and Web Applications and Services
Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
An efficient algorithm for time separation of events in concurrent systems
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Faster maximum and minimum mean cycle algorithms for system-performance analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing analysis of asynchronous systems using time separation of events
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Process variation-aware performance analysis of asynchronous circuits
Microelectronics Journal
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Asynchronous logic is an important topic due to its interesting features of high performance, low noise and robustness to parameters variations. However, its performance evaluation and optimization are relatively challenging processes due to the dependencies between concurrent events. This paper introduces a framework mainly in the context of performance driven synthesis of asynchronous circuits including systems with choice using buffer insertion technique. In the proposed framework, a high-level description of the system is received in Verilog format powered by some special macros, and then the corresponding specification will be decomposed into smaller circuits which is possible to be directly mapped into predefined circuit templates. The proposed flow has the advantage of exploiting a new performance metric and presents an efficient methodology for static estimation of average performance of asynchronous circuits with choices at the template level. The selected performance model is a probabilistic timed Petri-Net that includes probabilistic choice places to capture the conditional behavior of the system. Since there are no any data handling during the proposed static analyzing leads to very fast performance estimation with enough precise results. The buffer insertion technique is properly encoded in a quantum genetic algorithm and then is exploited after decomposition step during the synthesis flow. This algorithm addresses the problem of identifying the number and location of inserted buffers needed in an asynchronous circuit with choice to satisfy a given average case performance constraint, thereby implicitly minimizes the area for a given average case performance. Experimental results on a set of real systems indicate that our proposed technique can achieve a 34% performance enhancement in average by forcing a 19% area penalty.