Timed circuits: a new paradigm for high-speed design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Conformance and mirroring for timed asychronous circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Automatic Real-Time Analysis of Reactive Systems with the PARTS Toolset
Automated Software Engineering
Verification of Bounded Delay Asynchronous Circuits with Timed Traces
AMAST '98 Proceedings of the 7th International Conference on Algebraic Methodology and Software Technology
Partial Order Reduction for Model Checking of Timed Automata
CONCUR '99 Proceedings of the 10th International Conference on Concurrency Theory
Efficient Verification of Timed Automata Using Dense and Discrete Time Semantics
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Performance Analysis of Asynchronous Circuits Using Markov Chains
Concurrency and Hardware Design, Advances in Petri Nets
Timed Verification of Asynchronous Circuits
Concurrency and Hardware Design, Advances in Petri Nets
Automatic Abstraction for Verification of Timed Circuits and Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
CSL '99 Proceedings of the 13th International Workshop and 8th Annual Conference of the EACSL on Computer Science Logic
RAPPID: An Asynchronous Instruction Length Decoder
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Timed Trace Theoretic Verification Using Partial Order Reduction
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Verification of Delayed-Reset Domino Circuits Using ATACS
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A partial order semantics approach to the clock explosion problem of timed automata
Theoretical Computer Science - Tools and algorithms for the construction and analysis of systems (TACAS 2004)
Adding invariants to event zone automata
FORMATS'06 Proceedings of the 4th international conference on Formal Modeling and Analysis of Timed Systems
Symbolic unfoldings for networks of timed automata
ATVA'06 Proceedings of the 4th international conference on Automated Technology for Verification and Analysis
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