Modeling and Verification of Time Dependent Systems Using Time Petri Nets
IEEE Transactions on Software Engineering
Theoretical Computer Science
Representing and modeling digital circuits
Representing and modeling digital circuits
Timing analysis and verification of timed asynchronous circuits
Timing analysis and verification of timed asynchronous circuits
Symbolic Model Checking
Signal Graphs: From Self-Timed to Timed Ones
International Workshop on Timed Petri Nets
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Efficient verification using generalized partial order analysis
Proceedings of the conference on Design, automation and test in Europe
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Time supervision of concurrent systems using symbolic unfoldings of time petri nets
FORMATS'05 Proceedings of the Third international conference on Formal Modeling and Analysis of Timed Systems
Complete finite prefixes of symbolic unfoldings of safe time petri nets
ICATPN'06 Proceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency
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