Computer - IEEE Centennial: the state of computing
Spectral Techniques in Digital Logic
Spectral Techniques in Digital Logic
The theory of signature testing for VLSI
STOC '82 Proceedings of the fourteenth annual ACM symposium on Theory of computing
Testing by Verifying Walsh Coefficients
IEEE Transactions on Computers
A Note on Testing Logic Circuits by Transition Counting
IEEE Transactions on Computers
An Advanced Fault Isolation System for Digital Logic
IEEE Transactions on Computers
IEEE Transactions on Computers
Syndrome-Testable Design of Combinational Circuits
IEEE Transactions on Computers
Measures of the Effectiveness of Fault Signature Analysis
IEEE Transactions on Computers
Transition Count Testing of Combinational Logic Circuits
IEEE Transactions on Computers
Spectral Fault Signatures for Internally Unate Combinational Networks
IEEE Transactions on Computers
IEEE Design & Test
Built-In Self-Test Trends in Motorola Microprocessors
IEEE Design & Test
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks
IEEE Transactions on Computers
Optimal Robust Compression of Test Responses
IEEE Transactions on Computers
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
IEEE Transactions on Computers
Programmable BIST Space Compactors
IEEE Transactions on Computers
Determining Aliasing Probabilities in BIST by Counting Strings
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Board-level diagnosis by signature analysis
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
A new framework for designing & analyzing BIST techniques: computation of exact aliasing probability
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
The non-linear feedback shift-register as a built-in self-test (BIST) resource
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
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A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of time compression schemes with respect to errors detected are developed. The use of two or more of these methods together is considered. Methods to design efficient test compression structures for built-in-tests are proposed. The feasibility of the proposed approach is demonstrated by simulation results.