Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
A method for generating weighted random test pattern
IBM Journal of Research and Development
IBM Journal of Research and Development
A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
Module Level Weighted Random Patterns
Journal of Electronic Testing: Theory and Applications
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern Testing
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test Point Insertion for an Area Efficient BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Module level weighted random patterns
ATS '95 Proceedings of the 4th Asian Test Symposium
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Test point insertion based on path tracing
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Scan Latch Design for Test Applications
Journal of Electronic Testing: Theory and Applications
Distributed Diagnosis of Interconnections in SoC and MCM Designs
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Computers
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
IEEE Transactions on Computers
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This paper describes the design details, operation, cost, and performance of a distributed weighted pattern test approach at the chip level. The traditional LSSD SRLs are being replaced by WRP SRLs designed specifically to facilitate a weighted random pattern (WRP) test. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to 驴go after驴 the remaining untested faults. The cost and performance of this design system are explored on ten pilot chips. Results of this experiment are provided in the paper.