Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
| Hi-index | 0.00 |
The paper describes a module levelself-test architecture that uses weightedrandom patterns. A pseudorandom pattern generator (PRPG) is usedto generate equally likely patterns that are then transformed toweighted patterns by a universal weighting generator. The modulebeing tested is assumed to be composed of a number of chips all ofwhich have been designed to support a scan test. The signature iscollected by a multiple input signature register (MISR). Each scanlatch in the module is fed by its near-optimal weight duringtest. In order to avoid any additional test pins, some of theexisting signal pins are designated (demultiplexed) to perform aweight control function during test. This architecture candramatically decrease the self-test time with only a small increaseof hardware overhead.