Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IEEE Transactions on Computers
Probabilistic Treatment of General Combinational Networks
IEEE Transactions on Computers
IBM Journal of Research and Development
IEEE Transactions on Computers
Random Pattern Testability of Memory Control Logic
IEEE Transactions on Computers
On-Chip Weighted Random Patterns
Journal of Electronic Testing: Theory and Applications
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Techniques for Estimation of Design Diversity for Combinational Logic Circuits
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
10.3 Distributed Generation of Weighted Random Patterns
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Efficient Design Diversity Estimation for Combinational Circuits
IEEE Transactions on Computers
GlitchMap: an FPGA technology mapper for low power considering glitches
Proceedings of the 44th annual Design Automation Conference
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