Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IBM Journal of Research and Development
A structure and technique for pseudorandom-based testing of sequential circuits
Journal of Electronic Testing: Theory and Applications
PROTEST: a tool for probabilistic testability analysis
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant Circuits
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test Point Insertion for an Area Efficient BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Module level weighted random patterns
ATS '95 Proceedings of the 4th Asian Test Symposium
The Weighted Random Test-Pattern Generator
IEEE Transactions on Computers
Random-pattern coverage enhancement and diagnosis for LSSD logic self-test
IBM Journal of Research and Development
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A new weighted random pattern (WRP) design for testability (DFT) is described where the shift register latches (SRLs) distributed throughout the chip are modified so that they can generate biased pseudo-random patterns upon demand. A two-bit code is transmitted to each WRP SRL to determine its specific weight. The WRP test is then divided into groups, where each group is activated with a different set of weights. The weights are dynamically adjusted during the course of the test to "go after" the remaining untested faults.The cost and performance of this design system are explored on three pilot chips. Results of this experiment are provided in the paper.