Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On-Chip Weighted Random Patterns
Journal of Electronic Testing: Theory and Applications
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
10.3 Distributed Generation of Weighted Random Patterns
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
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The paper describes a module level self-test architecture that uses weighted random patterns. A pseudorandom pattern generator (PRPG) is used to generate equally likely patterns that are then transformed to weighted patterns by a universal weighting generator. The module being tested is assumed to be composed of a number of chips all of which have been designed to support a scan test. The signature as collected by a multiple input signature register (MISR). Each scan latch in the module is fed by its near-optimal weight during test. In order to avoid any additional test pins, some of the existing signal pins are designated (demultiplexed) to perform a weight control function during test. This architecture can dramatically decrease the self-test time with only a small increase of hardware overhead.