Random Pattern Testability of Memory Control Logic

Authors:
Jacob Savir
Affiliations:
New Jersey Institute of Technology, Newark, NJ
Venue:
IEEE Transactions on Computers
Year:
1998

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Abstract

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.