Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IBM Journal of Research and Development
Salvaging Test Windows in BIST Diagnostics
IEEE Transactions on Computers
Random Pattern Testability of Memory Control Logic
IEEE Transactions on Computers
Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Production Experience with Built-In Self-Test in the IBM ES/9000 System
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Design of an Efficient Weighted-Random-Pattern Generation System
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Deterministic Pattern Generation for Weighted Random Pattern Testing
EDTC '96 Proceedings of the 1996 European conference on Design and Test
BIST-based fault diagnosis in the presence of embedded memories
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Random pattern testability of memory address logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Of late some interesting and useful work has been done onthe problem of testing logic surrounding embedded memories. This workassumes that the logic surrounding the memory is functionallypartitioned and that the different partitions are logically isolatedone from the other. This paper expands upon past work using a moreflexible design rule which allows feed-forward connections betweenthe data-path Prelogic and Postlogic. The connections are such thatthere is no feedback from the memory outputs to its inputs, and boththe Prelogic and the Postlogic are disconnected from theAddress and Control logic. Under this design rule we show theauxiliary circuits used to determine the random patterntestability of faults in the circuitry driving the address inputsand the controls of the two-port memory. The techniquesdescribed herein are intended to be used in conjunction with thecutting algorithm for testability measurement in built-in self-test(BIST) designs, but may also be suitable for use with other detectionprobability tools and simulation tools.