Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Reduced Latch Count Shift Registers
Journal of Electronic Testing: Theory and Applications
Distributed Generation of Weighted Random Patterns
IEEE Transactions on Computers
Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Scan Latch Design for Delay Test
Proceedings of the IEEE International Test Conference
Delay Testing with Clock Control: An Alternative to Enhanced Scan
Proceedings of the IEEE International Test Conference
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Test generation systems in Japan
DAC '75 Proceedings of the 12th Design Automation Conference
Test generation for large logic networks
DAC '77 Proceedings of the 14th Design Automation Conference
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This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.