Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Overview of PowerPCTM 620 Multiprocessor Verification Strategy
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Scan Latch Design for Test Applications
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
This paper shows a new family of shift register designs which enjoysa reduced latch count. Reduction in the latch count is achieved byintroducing additional clocks. The reduction in latch count may reach theultimate savings of 50%.