Distributed Diagnosis of Interconnections in SoC and MCM Designs

Authors:
Rajesh Pendurkar;Abhijit Chatterjee;Yervant Zorian
Affiliations:
Sun Microsystems, 430 North Mary Avenue, Sunnyvale, CA 94085, USA. rajesh.pendurkar@sun.com;School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250, USA. chat@ee.gatech.edu;Virage Logic, Inc., 47100 Bayside Parkway, Fremont, CA 94538, USA. zorian@viragelogic.com
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2004

Citing 20
Cited 0

Built-in test for VLSI: pseudorandom techniques

Built-in test for VLSI: pseudorandom techniques
Synthesis of BIST hardware for performance testing of MCM interconnections

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Distributed Generation of Weighted Random Patterns

IEEE Transactions on Computers
Distributed BIST Architecture to Combat Delay Faults

Journal of Electronic Testing: Theory and Applications
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan

ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules

Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Achieving Board-Level BIST Using the Boundary-Scan Master

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Two-Pattern Test Capabilities of Autonomous TPG Circuits

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Testing the Enterprise IBM System/390TM Multi Processor

Proceedings of the IEEE International Test Conference
Delay test of chip I/Os using LSSD boundary scan

ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Test Methodology for VLSI Chips on Silicon

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A distributed BIST technique for diagnosis of MCM interconnections

ITC '98 Proceedings of the 1998 IEEE International Test Conference
Designing Self-Testable Multi-Chip Modules

EDTC '96 Proceedings of the 1996 European conference on Design and Test
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan

VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A Scalable,Low Cost Design-for-Test Architecture for UltraSPARC" Chip Multi-Processors

ITC '02 Proceedings of the 2002 IEEE International Test Conference
Design of efficient BIST test pattern generators for delay testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Switching activity generation with automated BIST synthesis for performance testing of interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On automatic-verification pattern generation for SoC with port-order fault model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic interconnection rectification for SoC design verification based on the port order fault model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

An interconnect test and diagnostic scheme based on distributed BIST resources in SOC and MCM designs is described. Test and diagnosis is enabled by embedding cascaded test pattern generators and reconfigurable signature analyzers into the design. The theory of partitioning of linear registers is applied to devise a two phase distributed diagnosis strategy. The design of a novel MISR reconfiguration scheme that enables high diagnosis resolution is presented.