Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Synthesis of BIST hardware for performance testing of MCM interconnections
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Achieving Board-Level BIST Using the Boundary-Scan Master
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Testing the Enterprise IBM System/390TM Multi Processor
Proceedings of the IEEE International Test Conference
A Test Methodology for VLSI Chips on Silicon
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
BIST TPGs for Faults in Board Level Interconnect via Boundary Scan
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Designing "Dual personality" IEEE 1149.1 compliant multi-chip modules
ITC'94 Proceedings of the 1994 international conference on Test
Distributed Diagnosis of Interconnections in SoC and MCM Designs
Journal of Electronic Testing: Theory and Applications
Agent-based test and repair of distributed systems
Journal of Embedded Computing - Low-power Embedded Systems
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A general description of an enhanced scheme fordesigning completely self-testable MCMs is given. Itallows performance testing and diagnosis of MCMinterconnections for dynamic effects. This scheme isbased on embedding of cascadable test pattern generatorsand reconfigurable signature analyzers into thedesign of MCM dies. A theory of partitioning of linearregisters is applied to devise a two phase distributeddiagnosis strategy. The design of a novel MISR reconfigurationscheme that enables high diagnosis resolution,is presented. Simulation results obtained confirm theeffectiveness of our BIST technique.