Distributed Diagnosis of Interconnections in SoC and MCM Designs
Journal of Electronic Testing: Theory and Applications
Rescue: A Microarchitecture for Testability and Defect Tolerance
Proceedings of the 32nd annual international symposium on Computer Architecture
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design for testability features of godson-3 multicore microprocessor
Journal of Computer Science and Technology
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An emerging trend in microprocessor architecture for servers is to design chips with multiple processor cores on a chip called Chip Multi-Processors (CMPs). Because of the short design cycle time and large size of these chips, the design-for-testability and testing of such chips is a big challenge. In this paper we describe a hierarchical DFT architecture for UltraSPARC驴 CMPs that is scalable with number of processor cores and can be implemented in a very short design cycle time. The DFT architecture allows testing of the processor cores individually for diagnosis as well as concurrently to reduce test application time and thus test cost. The DFT architecture can be easily ported across CMPs with different numbers of processor cores as well as to higher order CMPs designed by putting together CMPs.