JIAJIA: A Software DSM System Based on a New Cache Coherence Protocol
HPCN Europe '99 Proceedings of the 7th International Conference on High-Performance Computing and Networking
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor
ITC '02 Proceedings of the 2002 IEEE International Test Conference
A Scalable,Low Cost Design-for-Test Architecture for UltraSPARC" Chip Multi-Processors
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design
ITC '04 Proceedings of the International Test Conference on International Test Conference
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores
ITC '04 Proceedings of the International Test Conference on International Test Conference
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This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor, which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications. Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources. To achieve a scalable and flexible test access, a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes. Taking advantage of multiple identical cores embedding in the processor, scan partition and on-chip comparisons are employed to reduce test power and test time. Test compression technique is also utilized to decrease test time. To further reduce test power, clock controlling logics are designed with ability to turn off clocks of non-testing partitions. In addition, scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes, which poses low complexity and has good correlation results.