Synthesis of BIST hardware for performance testing of MCM interconnections
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BIST-Based Delay Path Testing in FPGA Architectures
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Distributed Diagnosis of Interconnections in SoC and MCM Designs
Journal of Electronic Testing: Theory and Applications
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Conventional built-in self-test (BIST) test pattern generators (TPGs) are designed to maximize stuck-at fault coverage in combinational circuits. Such TPGs often provide inadequate coverage of two-pattern tests which are required for the detection of delay faults. In this paper, theoretical results and procedures are presented to design efficient TPGs that ensure high two-pattern coverage for comprehensive delay testing of a circuit under test (CUT). First, new concepts particular to delay testing are identified and exploited to design efficient TPGs based on interleaved cyclic codes. A new concept of test cones is then introduced to further reduce the test length. Finally, the proposed procedures are used to design TPGs for delay testing of ISCAS'89 benchmark circuits and the results demonstrate their effectiveness