A BIST scheme for the detection of path-delay faults

Design for testability for path delay faults in sequential circuits

DAC '93 Proceedings of the 30th international Design Automation Conference

Statistical estimation of delay fault detectabilities and fault grading

Journal of Electronic Testing: Theory and Applications

A Multiple Seed Linear Feedback Shift Register

IEEE Transactions on Computers

BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms

IEEE Transactions on Computers

High-Performance Circuit Testing with Slow-Speed Testers

Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test

At-Speed Test is not Necessarily an AC Test

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner

Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner

Two-Pattern Test Capabilities of Autonomous TPG Circuits

Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner

An almost full-scan BIST solution-higher fault coverage and shorter test application time

ITC '98 Proceedings of the 1998 IEEE International Test Conference

PSBIST: A Partial-Scan Based Built-In Self-Test Scheme

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them

BIST and Delay Fault Detection

Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them

A logic design structure for LSI testability

DAC '77 Proceedings of the 14th Design Automation Conference

A graph approach to DFT hardware placement for robust delay fault BIST

VLSID '95 Proceedings of the 8th International Conference on VLSI Design

Design of efficient BIST test pattern generators for delay testing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems