A Unity Gain High Speed Buffer to Improve Signal Integrity in High Frequency Test Interface
Journal of Electronic Testing: Theory and Applications
Design for Delay Testability in High-Speed Digital ICs
Journal of Electronic Testing: Theory and Applications
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Journal of Electronic Testing: Theory and Applications
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers
Journal of Electronic Testing: Theory and Applications
Bridging the Testing Speed Gap: Design for Delay Testability
ETW '00 Proceedings of the IEEE European Test Workshop
11.2 Impedance Mismatch and Lumped Capacitance Effects in High Frequency Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testing High Speed VLSI Devices Using Slower Testers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
A DFT Technique for High Performance Circuit Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing high-performance pipelined circuits with slow-speed testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A digitally programmable delay element: design and analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
DFT for Delay Fault Testing of High-Performance Digital Circuits
IEEE Design & Test
DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low Voltage Test in Place of Fast Clock in DDSI Delay Test
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Synchronization overhead in SOC compressed test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths
Journal of Electronic Testing: Theory and Applications
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