High-Performance Circuit Testing with Slow-Speed Testers
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Correction to "A digitally programmable delay element: Design and analysis"
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A sige BiCMOS instrumentation channel for extreme environment applications
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
A VLSI for deskewing and fault tolerance in LVDS links
RTC'05 Proceedings of the 14th IEEE-NPSS conference on Real time
A continuous-time IR-UWB RAKE receiver for coherent symbol detection
Analog Integrated Circuits and Signal Processing
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Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Although, a few types of digitally controlled delay elements have been proposed, an analytical expression for the delay of these circuits has not been reported. In this paper, we propose a new delay element architecture and develop an analytical equation for the output voltage and an empirical relation for the delay of the circuit. The proposed circuit exhibits improved delay characteristics over previously reported digitally controlled delay elements.