Design for Delay Testability in High-Speed Digital ICs
Journal of Electronic Testing: Theory and Applications
High-Performance Circuit Testing with Slow-Speed Testers
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers
Journal of Electronic Testing: Theory and Applications
Testing High Speed VLSI Devices Using Slower Testers
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A DFT Technique for High Performance Circuit Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
High-Frequency, At-Speed Scan Testing
IEEE Design & Test
Testing high-performance pipelined circuits with slow-speed testers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transition Tests for High Performance Microprocessors
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
LOW OVERHEAD DELAY TESTING OF ASICS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Trends in Testing Integrated Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
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This article presents experimental results for a clock-timing methodology that allows timing characterization and testing of high-speed pipelined datapaths using slow-speed testers. The technique uses a clock-timing circuit to control the data flow in the pipeline in the test mode. Test results show that the design provides an average timing resolution of 52.9 ps in 0.18 μm CMOS technology. Results also demonstrate the ability of the technique to track the performance of high-speed pipelines at a reduced clock frequency and to test the clock-timing circuit used to generate and control test mode clocks.