Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
On Linear Dependencies in Subspaces of LFSR-Generated Sequences
IEEE Transactions on Computers
Delay Test Generation: A Hardware Perspective
Journal of Electronic Testing: Theory and Applications
Mixed-Mode BIST Using Embedded Processors
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
A mixed-mode BIST scheme based on folding compression
Journal of Computer Science and Technology
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Journal of Electronic Testing: Theory and Applications
A BIST scheme for the detection of path-delay faults
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Generator choices for delay test
ATS '95 Proceedings of the 4th Asian Test Symposium
A Gauss-elimination based PRPG for combinational circuits
EDTC '95 Proceedings of the 1995 European conference on Design and Test
On Using Machine Learning for Logic BIST
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Multiple test set generation method for LFSR-based BIST
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
| Hi-index | 14.99 |
The authors describe a design of an LFSR (linear feedback shift register) that can easily accommodate a change-of-seeds feature. This new LFSR is controlled by two separate clocks, one for the normal LFSR operation and one for the change of seeds option. The change of seeds is fast since it is accomplished by a pair of clock pulses rather than by long scan operations.