Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
AC strength of a pattern generator
Journal of Electronic Testing: Theory and Applications
A Multiple Seed Linear Feedback Shift Register
IEEE Transactions on Computers
Random Pattern Testability of Delay Faults
IEEE Transactions on Computers
At-Speed Test is not Necessarily an AC Test
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Skewed-Load Transition Test: Part 2, Coverage
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Distributed BIST Architecture to Combat Delay Faults
Journal of Electronic Testing: Theory and Applications
Scan Latch Design for Delay Test
ITC '97 Proceedings of the 1997 IEEE International Test Conference
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An important problem one faces during design of a built-in self-test (BIST) based delay test is the selection of a proper generator to apply the test vectors. This problem is due to the need of applying a pair of patterns to detect any given delay fault. The second vector has to be launched against the logic immediately following the first vector. This timing requirement places severe restrictions on the kind of hardware suitable for the task, especially in built-in self-test applications where the generator must reside on chip. This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. The different options are measured based on their performance, cost, and flexibility.