Pattern-based verification of connections to intellectual property cores
Integration, the VLSI Journal
Distributed Diagnosis of Interconnections in SoC and MCM Designs
Journal of Electronic Testing: Theory and Applications
High level equivalence symmetric input identification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
An automatic interconnection rectification technique for SoC design integration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A probabilistic analysis method for functional qualification under mutation analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Embedded cores are being increasingly used in the design of large system-on-a-chip (SoC). Because of the high complexity of SoC, the design verification is a challenge for system integrators. To reduce the verification complexity, the port-order fault (POF) model has been used for verifying core-based designs (Tang and Jou, 1998). In this paper, we present an automatic-verification pattern generation (AVPG) for SoC design verification based on the POF model and perform experiments on combinational and sequential benchmarks. Experimental results show that our AVPG can efficiently generate verification patterns with high POF coverage