Logic design principles with emphasis on testable semicustom circuits
Logic design principles with emphasis on testable semicustom circuits
Generalized Reed-Muller Forms as a Tool to Detect Symmetries
IEEE Transactions on Computers
Symmetry detection for incompletely specified functions
Proceedings of the 41st annual Design Automation Conference
Graph Automorphism-Based Algorithm for Determining Symmetric Inputs
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
K-disjointness paradigm with application to symmetry detection for incompletely specified functions
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
BDD minimization using symmetries
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On automatic-verification pattern generation for SoC with port-order fault model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast computation of symmetries in Boolean functions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Symmetric input identification is an important technique in logic synthesis. Previous approaches deal with this problem by building BDDs and developing algorithms to determine symmetric inputs. For the design whose corresponding BDDs cannot be built, BDD-based approaches cannot be applied on this problem. To avoid the limitations of BDD-based approaches, simulation-based methods have been proposed. It is applicable to designs described in arbitrary level, especially to high-level and black box designs. Previous simulation-based approaches focus on determining the inputs of nonequivalence symmetry. In this paper, we propose a simulation-based approach to identify equivalence symmetric inputs. The experimental results on a set of ISCAS-85 and MCNC benchmarks are also presented.